1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device.
2. Description of Related Art
A trench gate structure is generally known as a structure effective for refinement of a VDMOSFET (Vertical Double diffused Metal Oxide Semiconductor Field-Effect Transistor).
FIG. 9 is a schematic sectional view showing the structure of a conventional semiconductor device including a trench gate type VDMOSFET.
A semiconductor device 401 shown in FIG. 9 includes an N+-type (high-concentration N-type) substrate 402. An N−-type (low-concentration N-type) epitaxial layer 403 is laminated on the N+-type substrate 402. A base layer portion of the N−-type epitaxial layer 403 forms an N−-type region 404. A P−-type body region 405 is formed on a surface layer portion of the N−-type epitaxial layer 403 vertically adjacently to the N−-type region 404.
A first trench 406 and a second trench 407 smaller in width than the first trench 406 are formed in the N−-type epitaxial layer 403.
The first trench 406 is dug in the P−-type body region 405 from the surface thereof to penetrate through the P−-type body region 405, so that the deepest portion thereof reaches the N−-type region 404. A gate insulating film 408 made of SiO2 (silicon oxide) is formed in the first trench 406, to cover the inner surface thereof. A gate electrode 409 made of polysilicon (doped polysilicon) doped with an N-type impurity in a high concentration is embedded inside of the gate insulating film 408.
The second trench 407 is also dug in the P−-type body region 405 from the surface thereof to penetrate through the P−-type body region 405, so that the deepest portion thereof reaches the N−-type region 404. A gate insulating film 410 made of SiO2 is formed in the second trench 407, to cover the inner surface thereof. A gate electrode 411 made of doped polysilicon is embedded inside of the gate insulating film 410.
N+-type source regions 412 are formed on a surface layer portion of the P−-type body region 405. Further, P+-type body contact regions 413 are formed on a surface layer portion of the P−-type body region 405, to penetrate through the N+-type source regions 412.
A drain electrode 414 is formed on the back surface of the N+-type substrate 402.
An interlayer dielectric film (not shown) is laminated on the N−-type epitaxial layer 403. A gate wire (not shown) prepared from an Al (aluminum) alloy wire, for example, is formed on the interlayer dielectric film. In the interlayer dielectric film, a contact hole (not shown) is penetratingly formed on a portion where the gate wire and the gate electrode 409 are opposed to each other, so that the gate electrode 409 and the gate wire are in contact (electrically connected) with each other through this contact hole.
The gate electrodes 409 and 411 may be formed by filling up the first and second trenches 406 and 407 with non-doped polysilicon (polysilicon doped with no impurity) and implanting an impurity into this non-doped polysilicon respectively.
More specifically, an oxide film is formed on the surface of the N−-type epitaxial layer 403 including the inner surfaces of the first and second trenches 406 and 407. A deposition layer of non-doped polysilicon is formed on the oxide film, with a thickness for filling up the first trench 406. Thereafter the impurity is implanted into a surface layer portion of the deposition layer of non-doped polysilicon. After this implantation of the impurity, a heat treatment is performed. Thus, the deposition layer of non-doped polysilicon is converted to a deposition layer of doped polysilicon. Thereafter portions of the deposition layer of doped polysilicon located outside the first and second trenches 406 and 407 are removed by etch-back, so that the gate electrodes 409 and 411 made of doped polysilicon are formed in the first and second trenches 406 and 407 respectively.
However, the impurity is implanted from the surface of the deposition layer of non-doped polysilicon, and hence the impurity concentrations of the gate electrodes 409 and 411 are sloped to lower toward deep positions thereof. Therefore, the gate electrodes 409 and 411 disadvantageously exhibit relatively large resistances, due to low conductivities on the bottom portions thereof.
In order to solve this problem, the time for implanting the impurity may be so set as to sufficiently implant the impurity up to the bottom portions of the gate electrodes 409 and 411. In this case, however, an extremely long time is required for implanting the impurity.
On the other hand, the conductivities of the gate electrodes 409 and 411 may be increased by another method of forming the gate electrodes 409 and 411. According to this method, a deposition layer of doped polysilicon having a thickness for filling up the first trench 406 is formed on an oxide film provided on the surface of the N−-type epitaxial layer 403 by depositing polysilicon while doping the same with an impurity. Thereafter portions of the deposition layer of doped polysilicon located outside the first and second trenches 406 and 407 are removed by etch-back.
According to this method, however, silicon embeddability is deteriorated due to the width of the first trench 406 larger than that of the second trench 407. Therefore, a recess is formed on the surface of the deposition layer of doped polysilicon on a portion located above the wider first trench 406. The size of this recess is increased due to the step of etching back the deposition layer of doped polysilicon. Consequently, a large recess 415 is formed on the surface of the wider gate electrode 409, as shown in FIG. 9. When surface washing is performed by repeating oxidation and a hydrofluoric acid treatment after the formation of the gate electrode 409, the size of the recess 415 formed on the surface of the wide gate electrode 409 is further increased.
When the size of the recess 415 is increased, stress may be applied to the gate electrode 409 due to oxidation of the surface of the recess 415 in the surface washing, a crystal defect may be formed in the gate electrode 409. The crystal defect in the gate electrode 409 causes reduction in the source-drain withstand voltage.
When the large recess 415 is formed on the surface of the wider gate electrode 409, the distance from the surface of the interlayer dielectric film laminated on the N−-type epitaxial layer 403 to the surface of the gate electrode 409 is increased. If an etching time for forming the contact hole is set with reference to the surface of the N−-type epitaxial layer 403, therefore, the contact hole may not penetrate through the interlayer dielectric film, and a contact failure may be caused between the gate electrode 409 and the gate wire.
If the etching time for forming the contact hole is set with reference to the surface of gate electrode 409, on the other hand, the N−-type epitaxial layer 403 (the N+-type source regions 412 and the P+-type body contact regions 413) may be dug down to cause the so-called junction leak when other contact holes for contact with the N+-type source regions 412 and the P+-type body contact regions 413 are formed in the interlayer dielectric film along with this contact hole.
While the surface of the deposition layer of doped polysilicon may conceivably be planarized by CMP (chemical mechanical polishing) so that no recess is formed on the surface of the gate electrode 409, the working cost is disadvantageously increased in this case due to increase in the number of the manufacturing steps.
The problem of the contact failure or the junction leak is not restricted to the structure having the first and second trenches 406 and 407 different in width from each other, but may also arise in a structure having trenches identical in width to each other.
FIG. 10 is a schematic sectional view showing the structure of another conventional semiconductor device including a trench gate type VDMOSFET.
A semiconductor device 501 shown in FIG. 10 includes an N+-type (high-concentration N-type) substrate 502. An N−-type (low-concentration N-type) epitaxial layer 503 is laminated on the N+-type substrate 502. A base layer portion of the N−-type epitaxial layer 403 forms an N−-type region 504. A P−-type body region 505 is formed on a surface layer portion of the N−-type epitaxial layer 503 vertically adjacently to the N−-type region 504.
A trench 506 is formed in the N−-type epitaxial layer 503. The trench 506 is dug in the P−-type body region 505 from the surface thereof to penetrate through the P−-type body region 505, so that the deepest portion thereof reaches the N−-type region 504. A gate insulating film 507 made of SiO2 (silicon oxide) is formed in the trench 506, to cover the inner surface thereof. A gate electrode 508 made of polysilicon (doped polysilicon) doped with an N-type impurity in a high concentration is embedded inside of the gate insulating film 507.
N+-type source regions 509 are formed on a surface layer portion of the P−-type body region 505 along the trench 506. Further, P+-type body contact regions 510 are formed on a surface layer portion of the P−-type body region 505, to penetrate through the N+-type source regions 509.
An interlayer dielectric film (not shown) is laminated on the N−-type epitaxial layer 503. A gate wire (not shown) made of Al (aluminum), for example, is formed on the interlayer dielectric film. The gate wire is in contact (electrically connected) with the gate electrode 508 through a gate contact hole (not shown) formed in the interlayer dielectric film. Source wires (not shown) are electrically connected to the N+-type source regions 509 and the P+-type body contact regions 510 through source contact holes (not shown) formed in the interlayer dielectric film.
A drain electrode 511 is formed on the back surface of the N+-type substrate 502.
In order to manufacture the semiconductor device 501, a silicon oxide film is formed on the surface of the N−-type epitaxial layer 503 including the inner surface of the trench 506. A deposition layer of doped silicon is formed on the silicon oxide film. The deposition layer of doped silicon is formed with a thickness for filling up the trench 506 and covering portions of the silicon oxide film located outside the trench 506. Thereafter portions of the deposition layer of doped silicon located outside the trench 506 are removed by etch-back. Thus, the gate electrode 508 made of doped silicon is formed in the trench 506.
However, the deposition layer of doped silicon grows at the same rate on the overall surface of the N−-type epitaxial layer 503 including the side surface of the trench 506. Therefore, a recess is formed on a portion of the surface of the deposition layer of doped silicon located above the trench 506. The size of this recess is increased due to the step of etching back the deposition layer of doped silicon. Consequently, a large recess 512 is formed on the surface of the gate electrode 508, as shown in FIG. 10. When surface washing is performed by repeating oxidation and a hydrofluoric acid treatment after the formation of the gate electrode 508, the size of the recess 512 formed on the surface of the gate electrode 508 is further increased.
When the large recess 512 is formed on the surface of the gate electrode 508, the distance from the surface of the interlayer dielectric film laminated on the N−-type epitaxial layer 503 to the surface (recess 512) of the gate electrode 508 is increased. If an etching time for forming the gate contact hole is set with reference to the surface of the N−-type epitaxial layer 503, therefore, the gate contact hole may not penetrate through the interlayer dielectric film, and a contact failure may be caused between the gate electrode 508 and the gate wire.
If the etching time for forming the gate contact hole is set with reference to the bottom surface of the recess 512, on the other hand, the source contact holes for contact with the N+-type source regions 509 (or the P+-type body contact regions 510) may penetrate through the N+-type source regions 509 and reach the P−-type body region 505 when the same are formed in the interlayer dielectric film along with the gate contact hole, to disadvantageously cause the so-called junction leak.
A DTI (Deep Trench Isolation) technique is known as an element isolation technique for electrically isolating a region provided with a high withstand voltage element such as a high withstand voltage MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) from a region provided with another element when the high withstand voltage element and the other element are mixedly provided on a semiconductor substrate.
FIG. 11 is a schematic sectional view showing the structure of a conventional semiconductor substrate provided with a high withstand voltage element.
The semiconductor substrate is formed by a thick-film SOI (Silicon On Insulator) substrate 601, for example. The thick-film SOI substrate 601 has a structure obtained by laminating an N-type epitaxial layer 604 made of Si (silicon) on a P- or N-type silicon substrate 602 through a BOX (Buried Oxide) layer 603 made of SiO2 (silicon oxide).
A deep trench 605 in the form of a quadrangular ring in plan view is dug in the epitaxial layer 604 from the surface thereof. The deepest portion of the deep trench 605 reaches the BOX layer 603. The deep trench 605 is filled up with polysilicon 607 through an oxide film 606 made of SiO2. A high withstand voltage element (not shown) such as a high withstand voltage MOSFET is formed on a region surrounded by the deep trench 605.
Thus, in the semiconductor device to which the DTI technique is applied, a region surrounded by the deep trench 605 filled up with the polysilicon 607 serves as an element forming region isolated (dielectrically isolated) from the periphery thereof.
In the steps of manufacturing the semiconductor device, an impurity is implanted into the epitaxial layer 604 for forming an impurity diffusion region (source region of the high withstand voltage MOSFET or the like, for example) in the element forming region, and a heat treatment is thereafter performed for activating the impurity. Further, another heat treatment is performed for forming the oxide film 606. When these heat treatments are performed, difference is caused between the quantities of expansion of the epitaxial layer 604 and the oxide film 606 due to the difference between the thermal expansion coefficients of Si and SiO2, and stress resulting from this difference is concentrated on portions around the upper and lower ends of the deep trench 605 in the epitaxial layer 604. When the heat treatments are repeated, therefore, crystal defects resulting from stress concentration may be formed around the upper and lower ends of the deep trench 605 in the epitaxial layer 604.